LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE WORK.box;
USE WORK.debounce;
USE WORK.clock_div;

ENTITY project_inst IS

	PORT(CLOCK_50: IN STD_LOGIC := '0';
		KEY: IN STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
		LEDG: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
      LEDR: OUT STD_LOGIC_VECTOR (14 DOWNTO 0) := (OTHERS => '0');
      LCD_DATA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
		LCD_EN, LCD_RS, LCD_RW, LCD_ON, LCD_BLON: OUT STD_LOGIC := '0';
		L_PIN: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1);
      R_PIN: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1));

END project_inst;

ARCHITECTURE logic OF project_inst IS

COMPONENT box IS

    PORT(clock, start_test: IN STD_LOGIC := '0';
        l_pin: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1);
        r_pin: INOUT STD_LOGIC_VECTOR(7 DOWNTO 1);
		  works: OUT STD_LOGIC := '0';
		  LCD: OUT STD_LOGIC_VECTOR(12 DOWNTO 0));

END COMPONENT;

COMPONENT clock_div

	PORT(clock_50Mhz: IN	STD_LOGIC;
		clock_1MHz: OUT	STD_LOGIC;
		clock_100KHz: OUT	STD_LOGIC;
		clock_10KHz: OUT	STD_LOGIC;
		clock_1KHz: OUT	STD_LOGIC;
		clock_100Hz: OUT	STD_LOGIC;
		clock_10Hz: OUT	STD_LOGIC;
		clock_1Hz: OUT	STD_LOGIC);	

END COMPONENT;

COMPONENT debounce IS

	PORT(pb, clock_100Hz: IN STD_LOGIC;
        pb_debounced: OUT STD_LOGIC);

END COMPONENT;

SIGNAL s_db_key, s_clock_100Hz, s_clock_10Hz: STD_LOGIC := '0';
SIGNAL s_start_test: STD_LOGIC := '0';
SIGNAL LCD: STD_LOGIC_VECTOR(12 DOWNTO 0);

BEGIN

    s_start_test <=  NOT s_db_key;
	 
	 LCD_DATA(7 DOWNTO 0) <= LCD(7 DOWNTO 0);
	 LCD_EN <= LCD(8);
	 LCD_RS <= LCD(9);
	 LCD_RW <= LCD(10);
	 LCD_ON <= LCD(11);
	 LCD_BLON <= LCD(12);

    LEDR(1) <= L_PIN(1);
    LEDR(2) <= L_PIN(2);
    LEDR(3) <= L_PIN(3);
    LEDR(4) <= L_PIN(4);
    LEDR(5) <= L_PIN(5);
    LEDR(6) <= L_PIN(6);
    LEDR(7) <= L_PIN(7);
    LEDR(8) <= R_PIN(7);
    LEDR(9) <= R_PIN(6);
    LEDR(10) <= R_PIN(5);
    LEDR(11) <= R_PIN(4);
    LEDR(12) <= R_PIN(3);
    LEDR(13) <= R_PIN(2);
	 LEDR(14) <= R_PIN(1);

    cd: clock_div
    PORT MAP(clock_50Mhz=>CLOCK_50, clock_10Hz=>s_clock_10Hz, clock_100Hz=>s_clock_100Hz);
	 
    deb: debounce
    PORT MAP(pb=>KEY(0), clock_100Hz=>s_clock_100Hz, pb_debounced=>s_db_key);

    testador:box
    PORT MAP(clock=>s_clock_100Hz, start_test=>s_start_test, l_pin(7 DOWNTO 1)=>L_PIN(7 DOWNTO 1), 
        r_pin(7 DOWNTO 1)=>R_PIN(7 DOWNTO 1), works=>LEDG(0), LCD=>LCD);
 
END logic;

    